View SMT4004_2776187.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 characteristics subject to change without notice 2049 2.2 9/13/00 SMT4004 summit microelectronics, inc. ?summit microelectronics, inc., 2000 ? 300 orchard city dr., suite 131 campbell, ca 95008 phone 408-378-6461 fax 408-378-6586 www.summitmicro.com programmable voltage and current monitoring monitors 4 independent supplies programmable host-side under- and over- voltage thresholds programmable card-side under-voltage monitors programmable card-side circuit breaker delay and quicktrip? threshold levels programmable card-side trakker function programmable slew rate control guarantees and enforces supply differential tracking distributed power hot-swap controller functional block diagram features programmable watchdog and longdog timers (0 to 6.4 seconds) operates from any one of four supply voltages nonvolatile fault register records source of any interrupt readable in ?dead board? environment all communications to configuration registers and memory array are via 2-wire serial inter- face supply manager #1 supply manager #2 supply manager #3 supply manager #4 vo1 cb1 vi1 vo3 cb3 vi3 vo2 cb2 vi2 vo4 cb4 vi4 rst1# rst2# rst3# rst4# crowbar cbfault healthy# vgate1 vgate2 vgate3 vgate4 vgg_cap enable trkr_irq# a0 a1 a2 sda scl wldi ldo# wdo# reset & status output control logic charge pump & vgate control timer logic memory & 2-wire bus interface trakker logic power supply arbitration sequence enable logic uv_override seated1# pwr_on seated2# force_sd irq_clr# mr# 1.25v ref agnd pgnd pgnd dgnd vdd_cap 10 1 16 15 11 2 12 3 24 6 13 4 14 5 19 9 8 7 18 17 26 25 29 27 28 31 32 33 42 43 46 44 45 47 48 30 20 37 41 21 36 40 22 35 39 23 34 38 irq# 2049 bd 2.1
2 SMT4004 2049 2.2 9/13/00 summit microelectronics, inc. * comment stresses listed under absolute maximum ratings may cause perma- nent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. temperature under bias ....................... -55c to 125c storage temperature ............................ -65c to 150c lead solder temperature (10 secs) ................... 300 c terminal voltage with respect to gnd: v 0 , v 1 , v 2 , and v 3 ........... -0.3v to 6.0v all others ........................ -0.3v to 6.0v pin configuration description absolute maximum ratings* the SMT4004 is a fully integrated programmable voltage manager ic, providing supervisory functions and tracking control for up to four independent power supplies. the four internal managers perform the following functions: monitor source (bus-side) voltages for under- and over- voltage conditions, monitor each supply for over-current conditions, monitor back end (card-side) voltages for two staged levels of under-voltage conditions, insure power to the card-side logic tracks within the specified parametric limits, and provide supply status information to a host processor. the SMT4004 incorporates nonvolatile programmable circuits for setting all of the monitored thresholds for each manager. individual functions are also programmable allowing interrupts or reset conditions to be generated by any combination of events. because of a proprietary eeprom technology that it employs it is also able to store fault conditions as they occur. in the case of a catastrophic failure the fault is recorded in the registers and then can be read for analysis. ldo# wdo# crowbar 1.25v ref mr# irq_clr# irq# pgnd trkr_irq# seated1# seated2# uv_override cb2 cb3 cb4 pwr_on vgate1 vgate2 vgate3 vgate4 v gg _cap force_sd healthy# cbfault 48-pin tqfp 2049 pcon 2.1 rst1# rst2# rst3# rst4# pgnd dgnd agnd vo1 vo2 vo3 vo4 enable wldi scl sda a2 a1 a0 v dd _cap vi1 vi2 vi3 vi4 cb1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37
3 2049 2.2 9/13/00 SMT4004 summit microelectronics, inc. dc operating characteristics ( over recommended operating conditions; voltages are relative to gnd ) 2049 elect table 1.0 l o b m y sr e t e m a r a ps e t o n. n i m. p y t. x a ms t i n u i v4 i v h g u o r h t 1 i v s e g a t l o v y l p p u s ( i v t s e h g i h e h t s r e w o p ) v 7 . 2 4 0 0 4 t m s 7 . 25 . 5v i d d n o t n e r r u c y l p p u s r e w o p e v i t c a e l b a n e d n a n o _ r w p13a m i d d f f oe v i t c a n i e l b a n e1 . 0a m p t i v d l o h s e r h t t u p n i i v e l b a m m a r g o r p e g n a r t i b / v m 0 2 , n o i t u l o s e r t i b - 89 . 00 . 6v i v s y h s i s e r e t s y h p i r t v u / v o 0 1v m v b c e g a t l o v p i r t r e k a e r b t i u c r i c0 25 20 3v m b c y a l e d r e t l i f t n e r r u c - r e v o . e l b a m m a r g o r p , b 1 r r e t s i g e r y b t e s , 0 d & 1 d s t i b a t a d y l e v i t c e p s e r 00 5 2s 01 0 5s 10 0 0 1s 11 0 0 2s v b c q e g a t l o v p i r t - k c i u q . e l b a m m a r g o r p , a 1 r r e t s i g e r y b t e s 6 d & 7 d s t i b a t a d ( . g . e y l e v i t c e p s e r , ) 00 f f o 01 5 7v m 10 0 0 1v m 11 0 5 1v m v f e r v 5 2 . 1 f e r e g a t l o v t u p t u or d a o l k 2 = ? 3 2 . 15 2 . 17 2 . 1v v g v n o e g a t l o v t u p t u o e v i r d e t a g v n o s e h c t i w s t e f s o m4 16 1v v g v f f og v k n i s a m 1 =04 . 0v i g v t n e r r u c t u p t u o e v i r d e t a g vn o s e h c t i w s t e f s o m0 8a r s g v e t a r w e l s e g a t l o v t u p t u o e t a g v . e l b a m m a r g o r p , 0 1 r r e t s i g e r y b t e s r o 2 d & 3 d s t i b a t a d y l e v i t c e p s e r , 0 d & 1 d 00 0 0 1s / v 01 0 5 2s / v 10 0 0 5s / v 11 0 0 0 1s / v r s a t l e d l a i t n e r e f f i d w e l s r e k k a r t l a i t n e r e f f i d a t l e d , s n i p o v d e w o l l a 0 0 1v m p t v o e g a t l o v e d i s - d r a c e l b a m m a r g o r p e g n a r d l o h s e r h t t i b / v m 0 2 , n o i t u l o s e r t i b - 89 . 00 . 6v v o s y h s i s e r e t s y h t u p n i v o 0 1v m v h i e g a t l o v h g i h t u p n i v 7 . 2 = i v9 . 0 i vi vv v 5 = i v7 . 0 i vi vv v l i e g a t l o v w o l t u p n i v 7 . 2 = i v1 . 0 ? 1 . 0 i vv v 5 = i v1 . 0 ? 3 . 0 i vv v l o s t u p t u o n i a r d n e p oi k n i s a m 2 =04 . 0v t w o r c h t d i w e s l u p t u p t u o r a b w o r ck 1 o t n i . n i m v 5 . 2 ? 457 s
4 SMT4004 2049 2.2 9/13/00 summit microelectronics, inc. pin descriptions and device operation the trakker supply voltages the vi inputs of all four supply managers are diode ored and tied to the device's internal v dd node. the trakker will use the highest vi input for its supply voltage. at least one vi input must be at or above 2.7v for proper device operation. v dd _cap ? charge storage connection for the chip's internal power suply. for most applications a 10f capacitor should be connected to his pin. v gg _cap ? this pin should be tied to a capacitor to be charged by the charge pump. the capacitor should be of sufficient size so as to provide current to the vgate outputs under varying load conditions. pgnd ? power ground dgnd ? digital ground agnd ? analog ground timers ldo# ? the longdog timer output is an active-low open- drain output that can be wire-ored with other open-drain signals. the longdog timer is generally programmed to generate an output at a time interval longer than the watchdog timer. the time interval is programmed in register r1c . wdo# ? the watchdog timer output is an active-low open-drain output that can be wire-ored with other open- drain signals. the watchdog timer is generally pro- grammed to generate an output at a time interval shorter than the longdog timer. the time interval is programmed in register r1c . wldi ? watchdog and longdog timer reset input. a low- to-high transition on this pin will reset both the watchdog timer and the longdog timer. the watchdog and longdog work in tandem: resetting one resets the other. generally, the longdog will be pro- grammed to time out sometime after the watchdog. as an example, the wdo# output could be used to generate a warning interrupt and the ldo# output could be tied to a system reset line. both timers can be turned off, facilitating system debug and also allowing operating systems to ? boot up ? and configure themselves without interrupts or resets. supply managers the electrical placement of the SMT4004 on a printed circuit card is such that it separates the host power supply and any on-board dc-to-dc converters (or ldos) from the backend circuitry such as multiple dsps, micropro- cessors and associated glue logic. the host supplies, and any other regulated voltages that will be ? switched ? by the device, are referred to as bus-side voltages. the voltages that are on the backend circuitry side of the switches are referred to as card-side voltages. the four supply manager blocks are identical. each contains three primary functional blocks: the first monitors the bus-side voltages, the second monitors the card-side voltages, and the third monitors over-current conditions for that particular supply. bus-side management figure 1 illustrates the functional blocks of the four supply managers. each manager block can be independently enabled or electrically removed from the device. the vi input monitors the bus-side voltage for both under- voltage and over-voltage conditions. the thresholds for the under-voltage detection for vi inputs are programmed in registers r00 through r03 . the vi input is effectively the v ref of a nonvolatile dac. the dac has been designed so that the threshold can be determined by multiplying the binary value of the register times 20mv and adding that to 0.9v in the formula p vit = 0.9v + (0.2mv n ), where n is the register value (0 - 255 decimal). this allows very precise monitoring of voltages in the range of 0.9v to 6v without the use of external resistor divider networks. the over-voltage section works in a similar manner, with the formula being offset = (p vit 1.2) + [(0.04 p vit ) n ], where n is the register value in r04 through r07 . all enabled manager blocks must ensure their respective vi inputs are within the programmed limits before the vgate outputs can be turned on and the trakker logic en- abled. the vi comparator outputs can also be used to generate a general interrupt. it should be noted that either one or both of the bus-side monitors could be disabled via registers r04 through r07 .
5 2049 2.2 9/13/00 SMT4004 summit microelectronics, inc. card-side management on the card-side the trakker monitors two program- mable under-voltage thresholds on the vo inputs: uv1 and uv2. uv1 can be used to generate a warning interrupt that the supply is decaying, and uv2 can be used to generate a reset condition or a crowbar output. the card- side under-voltage (uv1) threshold value is programmed in registers r08 through r0b . like the bus-side thresh- olds the levels can be programmed in 20mv increments (on top of 0.9v). the second level (uv2) is determined by the formula uv2 = uv1 ? [(uv1 0.01) n ], where n is the value in registers r0c through r0f . it should be noted that either one or both of the card-side monitors can be disabled via registers r0c through r0f . over-current protection the cb inputs are the circuit breaker inputs for the supply voltages. with a series resistor placed in the supply path between vi and cb the circuit breaker will trip whenever the voltage across the resistor exceeds 25mv. figure 1. supply manager circuit ? + + ? v ref + ? 25mv + ? ? + v ref programmable quick trip threshold programmable delay + ? vo x cb x vi x ov uv vgate enable oc quick trip to crowbar to irq to rst vgate and trakker logic ( = programmable) 2049 fig01 1.0 comparator comparator circuit breaker comparator uv1 comparator uv2 comparator quick trip comparator
6 SMT4004 2049 2.2 9/13/00 summit microelectronics, inc. the on-board electronic circuit breaker can be pro- grammed to application specific levels. the circuit breaker delay defines the period of time the voltage drop across r s is greater than 25mv but less than v qcb before the vgate output will be shut down. this is effectively a filter to prevent spurious shutdowns of vgate. the delays that can be programmed are 25s, 50s, 100s and 200s. the programmable delay bits are located in register r1b . the quick-trip circuit breaker threshold (v qcb ) can be set to 150mv, 100mv, 75mv or off (register r1a ). this is the threshold voltage drop across r s that is placed between v ss and cbsense. if the voltage drop exceeds the programmed threshold, the electronic circuit breaker will immediately trigger with no delay. the outputs of these comparators can be used to generate interrupts and reset conditions and toggle the crowbar output. power-on sequencing in order to begin sequencing of the card-side supplies (ramping the vgate outputs) a number of conditions must be met. all enabled bus-side voltages must be above their respective under-voltage thresholds, the card-side voltages ( e.g. , residual capacitor stored potentials) must be near zero volts , and the following inputs must be properly set . enable ? when active the enable input brings the ic out of a standby mode where the charge pump supplying the vgate outputs is turned on (and begins charging the vgg_cap) and the bandgap reference is turned on. the enable input can be programmed to be either active low (default from the factory) or active high (register r1b ). seated1# and seated2# ? the seated inputs are effectively two additional enable inputs that must be low to enable the sequencing of the card-side voltages. in a staggered pin environment these inputs can be tied to the ? short ? pins, insuring the card is fully seated before any power is applied to the card- side logic. these inputs can also be tied to card insertion switches to indicate proper seating. pwr_on ? the pwr_on input is the last input that will typically be driven to enable power sequencing to the card-side. the pwr_on input can be pro- grammed to be either active low (default from the factory) or active high (register r1b ). trakking and softstart control vgate ? the vgate outputs are used to control the ? turning-on ? of the card-side voltages. the ramp rate (for both turn-on and turn-off) of the outputs is programmable from 100v/s to 1000v/s (register r10 ). the four outputs ramp at the same slew-rate, so normally there will be no differential voltage between any of the supplies until each reaches its maximum level. the ramp rates are inherently adaptive. that is, if the difference between any vo input is greater than 100mv in the linear region, the slew rate will be increased or de- creased to minimize the differential. the comparisons are made between vo1 and vo2, vo2 and vo3, vo3 and vo4, and vo4 and vo1. if at any time a differential of greater than 300mv is detected a pre-programmed (reg- ister r10 ) action can be taken. the trakker can shut down the offending supply, generate an interrupt output, or ignore the situation. if softstart is enabled (registers r0c through r0f ) the supply or supplies designated will be ramped as soon as the input conditions are met and no trakking will be performed. any supply not designated as a softstart supply will not be ramped until the designated supply has reached its vo threshold. this type of operation would commonly be used where a bus voltage ( e.g. , 5v) is first switched to a dc-to-dc converter or group of ldos; and then their outputs would be switched in a trakking mode to the card-side logic. supply managers designated for trakking will not begin start-up until the soft start channels are fully turned on. the delay is approximated by the formula t d =16,000 sr, where t d is the time delay in milliseconds between the pwr_on signal going high and the start of the tracking ramp-up, and sr is the programmed start-up slew rate in v/s. for example, the time delay for a programmed slew rate of 500v/s is: t d = 16,000 500 = 32ms. power management status outputs the trakker has two types of status outputs that it provides to the host system or host processor resident on its board. one type of output is ? hardwired ? internally and the other is programmable. healthy# ? the healthy output is an active-low open-drain output that can be wire-ored with other open- drain signals. it is driven low when all of the enabled managers ? card-side voltages are valid and there are no over-current conditions. the signal is used to indicate the power supplies are within their programmed operating limits.
7 2049 2.2 9/13/00 SMT4004 summit microelectronics, inc. cbfault ? cbfault is driven active whenever an over-current condition is detected. it is a programmable output that can be either an active high or active low (factory default) output. resets rst1# to rst4# ? associated with each manager is a reset output. they are active-low open-drain outputs that can be wire-ored with other open-drain signals. the user can select uv1, uv2 and/or an over-current condition as the trigger for the reset pulse by programming registers r11 and r12 (the default condition from the factory is all conditions generate a reset). the reset pulse width is adjustable by writing to register r1c (default condition from the factory is pulse of 200ms). mr# ? when driven low the manual reset input will automatically drive all four reset outputs low. interrupts irq# ? the irq output is an active low open-drain output that is driven low whenever one or more of its programmed triggers is active. there are twenty programmable sources for generating the interrupt: bus-side over- and under-voltage, card-side under-voltage 1 and 2, and an over-current condition. each source is individually en- abled by writing to registers r13, r14 and r15 . the default from the factory is to enable all sources. the irq# output can only be cleared by bringing irq_clr# low, or after a power-down/power-up sequence. trkr_irq# ? the trakker interrupt indicates there was a skew of greater than 300mv during the power on cycle. the source of the trkr_irq# is programmable and can be initiated by any one of the managers. the configuration registers r11 and r12 select the source of interrupt. configuration register r10 enables the trkr_irq# output (or one of three other options). the default from the factory is to enable all sources. the trkr_irq # output can only be cleared by bringing irq_clr high or after a power-down/power-up se- quence. in order to avoid false interrupts during a power-on se- quence there is a programmable ? power-on interrupt hold- off ? register. the delay can be programmed from 200ms to 1600ms. the interrupt hold-off is in register r15 and its default value from the factory will be 1600ms. fault register whenever an interrupt is generated the cause of the fault will be recorded in the nonvolatile status register. in order to avoid false recordings during power-down situations, no faults will be recorded if the pwr_on input has been deactivated. the fault registers are located at r1d through r1f . the fault source is indicated by a ? 1 ? in the assigned bit location. overwriting the fault register with ? 0 ? s ? is the only way to clear a recorded fault condition. crowbar ? the crowbar output is another form of status output. the conditions to generate a crowbar output are programmable in register r19 . whenever one of the conditions occurs the crowbar output will strobe. rapid shutdown of the card-side supplies may be required to prevent damage to the dsp ? s or microprocessors. scrs with a fast turn-on time make excellent crowbar devices and only need a pulse of gate current to ? trigger. ? memory and register access a0, a1 & a2 ? the address pins are biased either to the highest vi pin or gnd, and provide a mechanism for assigning a unique address to the smh4004. sda ? sda is a bidirectional serial data pin. it is configured as an open drain output and will require a pull- up to the highest vi pin. scl ? scl is the serial clock input. miscellaneous manager signals 1.25v ref ? this pin is a 1.25v reference output that can be used in conjunction with external circuitry. uv_override ? the under-voltage override input will disable the under-voltage comparators. this can be used for board test and also during system margining. force_sd ? when asserted the force shut down input will immediately clamp the vgate outputs to ground. this can be used in conjunction with the crowbar . the active level for force_sd is programmable and acces- sible in register r1b .
8 SMT4004 2049 2.2 9/13/00 summit microelectronics, inc. register formats and functions there are four basic register types. the first are those that set a monitoring threshold where the binary value written to the register is multiplied times the base incremental voltage. the second type enables or disables a specific function: unless otherwise indicated a ? 1 ? will always enable the function and a ? 0 ? will disable or deselect that function. note : only the enabled condition will be depicted in the following tables. the third register type allows selection of various timer values. these are not incremen- tal, like the thresholds, but specific bit patterns select specific timer values. the fourth register type is the nonvolatile fault register that records fault conditions. a ? 0 ? in any bit location indicates its corresponding monitor function was within specified limits when the fault oc- curred. a ? 1 ? in any bit location indicates its corresponding monitor function was outside its specified limits when the fault occurred. bus-side under-voltage threshold registers 00 , 01 , 02 and 03 are identical. their contents select the under-voltage threshold for the vi1, vi2, vi3 and vi4 inputs, respectively. 3 0 r , 2 0 r , 1 0 r , 0 0 r r e t s i g e r 7 d6 d5 d4 d3 d2 d1 d0 dn o i t c a 11111111 v 0 . 6 = t n e m t s u j d a d l o h s e r h t t s e h g i h 00000000 v 9 . 0 = t n e m t s u j d a d l o h s e r h t t s e w o l 000000 10 2 ( + v 9 . 0 = d l o h s e r h t , v 4 9 . 0 = ) v 2 0 . . g . e 2049 table01 1.0 bus-side under-voltage threshold enable and over-voltage offset registers 04 , 05 , 06 and 07 are identical. their contents determine whetheror not the under- or over-voltage capa- bilities are enabled, and establish the over-voltage offset value for the vi1, vi2, vi3 and vi4 inputs, respectively. 7 0 r , 6 0 r , 5 0 r , 4 0 r r e t s i g e r 7 d6 d5 d4 d3 d2 d1 d0 dn o i t c a x 1 xxxxxx n o i t c e t e d e g a t l o v r e d n u s e l b a n e xx 1 xxxxx n o i t c e t e d e g a t l o v r e v o s e l b a n e xxx 000 10 i v ( = d l o h s e r h t d l o h s e r h t ( + ) % 0 2 + n i v 4 0 . d l o h s e r h t e r e h w ) n e u l a v y r a n i b r e t s i g e r = 2049 table02 1.0 card-side under-voltage threshold registers 08 , 09 , 0a and 0b are identical. their contents select the under-voltage threshold for the vo1, vo2, vo3 and vo4 inputs, respectively. b 0 r , a 0 r , 9 0 r , 8 0 r r e t s i g e r 7 d6 d5 d4 d3 d2 d1 d0 dn o i t c a 11111111 v 0 . 6 = t n e m t s u j d a d l o h s e r h t t s e h g i h 00000000 v 9 . 0 = t n e m t s u j d a d l o h s e r h t t s e w o l 000000 10 2 ( + v 9 . 0 = d l o h s e r h t , v 4 9 . 0 = ) v 2 0 . . g . e 2049 table03 1.0
9 2049 2.2 9/13/00 SMT4004 summit microelectronics, inc. card- side under-voltage threshold enable and over-voltage offset registers 0c , 0d , 0e and 0f are identical these registers will either enable or disable their associated power man- agement functions and soft start capability. their contents also determine whether the under- or over-voltage capa- bilities are enabled and the contents establish the over- voltage offset value for the vo1, vo2, vo3 and vo4 inputs, respectively. f 0 r , e 0 r , d 0 r , c 0 r r e t s i g e r 7 d6 d5 d4 d3 d2 d1 d0 dn o i t c a 1 xxxxxxx d e l b a n e l e n n a h c t n e m e g a n a m r e w o p x 1 xxxxxx g n i k k a r t e l b a n e = 0 ; t r a t s t f o s e l b a n e = 1 xx 1 xxxxx 2 e g a t l o v r e d n u s e l b a n e xxx 000 10 ( ? ) 1 v u ( = d l o h s e r h t n 1 v u e r e h w ) 1 0 . 0 n e u l a v y r a n i b r e t s i g e r = 2049 table04 1.0 addressing and slew rate control configuration register 10 is used to configure the ad- dressing protocol for the trakker . bit 7 determines whether the device will respond with an acknowledge to any bus request addressing its device type identifier, or whether it will be selective and only respond if the a2, a1 and a0 bits match the biasing of the external pins. bit 6 selects the device type identifier to be used for the memory array. 0 1 r r e t s i g e r 7 d6 d5 d4 d3 d2 d1 d0 dn o i t c a 0 x x s u b d e s a i b n i p o t y l n o s d n o p s e r s e s s e r d d a 1 x s e s s e r d d a s u b l l a o t s d n o p s e r x 0 0 1 0 1 r e i f i t n e d i e p y t - e c i v e d y r o m e m x 1 1 1 0 1 r e i f i t n e d i e p y t - e c i v e d y r o m e m n o i t c a l a i t n e r e f f i d v m 0 0 3 r e d n u / r e v o r e k k a r t x 00 x e r o n g i 01 d n a y l p p u s y t l u a f e h t n w o d t u h s # q r i _ r k r t 10 d n a s e i l p p u s l l a n w o d t u h s # q r i _ r k r t 11 # q r i _ r k r t e t a r e n e g ) n o o t f f o ( h g i h o t w o l e t a r w e l s r e k k a r t x 00 x s / v 0 0 1 01 s / v 0 5 2 10 s / v 0 0 5 11 s / v 0 0 0 1 ) f f o o t n o ( w o l o t h g i h e t a r w e l s r e k k a r t x 00 s / v 0 0 1 01 s / v 0 5 2 10 s / v 0 0 5 11 s / v 0 0 0 1 2049 table05 1.0
10 SMT4004 2049 2.2 9/13/00 summit microelectronics, inc. reset source select and trakker irq select (for supply managers 1 and 2) reset source select and trakker irq select (for supply managers 3 and 4) 1 1 r r e t s i g e r 7 d6 d5 d4 d3 d2 d1 d0 d n o i t c a 1 - 1 o v2 - 1 o vo 1 i v1 r k r t1 - 2 o v2 - 2 o vo 2 i v2 r k r t 1 xxxxxxx 1 # t s r s a 1 v u 1 e d i s - d r a c s t c e l e s r e g g i r t x 1 xxxxxx 1 # t s r s a 2 v u 1 e d i s - d r a c s t c e l e s r e g g i r t xx 1 xxxxx r e g g i r t 1 # t s r s a 1 i b c s t c e l e s xxx 1 xxxx t p u r r e t n i n a s a r o r r e 1 k r t s t c e l e s e c r u o s xxxx 1 xxx 2 # t s r s a 1 v u 2 e d i s - d r a c s t c e l e s r e g g i r t xxxxx 1 xx 2 # t s r s a 2 v u 2 e d i s - d r a c s t c e l e s r e g g i r t xxxxxx 1 xr e g g i r t 2 # t s r s a 2 i b c s t c e l e s xxxxxxx 1 t p u r r e t n i n a s a r o r r e 2 k r t s t c e l e s e c r u o s 2 1 r r e t s i g e r 7 d6 d5 d4 d3 d2 d1 d0 d n o i t c a 1 - 3 o v2 - 3 o vo 3 i v3 r k r t1 - 4 o v2 - 4 o vo 4 i v4 r k r t 1 xxxxxxx 3 # t s r s a 1 v u 3 e d i s - d r a c s t c e l e s r e g g i r t x 1 xxxxxx 3 # t s r s a 2 v u 3 e d i s - d r a c s t c e l e s r e g g i r t xx 1 xxxxx r e g g i r t 3 # t s r s a 3 i b c s t c e l e s xxx 1 xxxx t p u r r e t n i n a s a r o r r e 3 k r t s t c e l e s e c r u o s xxxx 1 xxx 4 # t s r s a 1 v u 4 e d i s - d r a c s t c e l e s r e g g i r t xxxxx 1 xx 4 # t s r s a 2 v u 4 e d i s - d r a c s t c e l e s r e g g i r t xxxxxx 1 xr e g g i r t 4 # t s r s a 4 i b c s t c e l e s xxxxxxx 1 t p u r r e t n i n a s a r o r r e 4 k r t s t c e l e s e c r u o s 2049 table06 1.0 2049 table07 1.0
11 2049 2.2 9/13/00 SMT4004 summit microelectronics, inc. irq source select (for supply managers 1 and 2) irq source select (for supply managers 3 and 4) 3 1 r r e t s i g e r 7 d6 d5 d4 d3 d2 d1 d0 d n o i t c a v o - 1 i vv u - 1 i v1 - 1 o v2 - 1 o vv o - 2 i vv u - 2 i v1 - 2 o v2 - 2 o v 1 xxxxxxx # q r i n a s a v o 1 e d i s - s u b s t c e l e s r e g g i r t x 1 xxxxxx # q r i n a s a v u 1 e d i s - s u b s t c e l e s r e g g i r t xx 1 xxxxx # q r i n a s a 1 v u 1 e d i s - d r a c s t c e l e s r e g g i r t xxx 1 xxxx # q r i n a s a 2 v u 1 e d i s - d r a c s t c e l e s r e g g i r t xxxx 1 xxx # q r i n a s a v o 2 e d i s - s u b s t c e l e s r e g g i r t xxxxx 1 xx # q r i n a s a v u 2 e d i s - s u b s t c e l e s r e g g i r t xxxxxx 1 x # q r i n a s a 1 v u 2 e d i s - d r a c s t c e l e s r e g g i r t xxxxxxx 1 # q r i n a s a 2 v u 2 e d i s - d r a c s t c e l e s r e g g i r t 4 1 r r e t s i g e r 7 d6 d5 d4 d3 d2 d1 d0 d n o i t c a v o - 3 i vv u - 3 i v1 - 3 o v2 - 3 o vv o - 4 i vv u - 4 i v1 - 4 o v2 - 4 o v 1 xxxxxxx # q r i n a s a v o 3 e d i s - s u b s t c e l e s r e g g i r t x 1 xxxxxx # q r i n a s a v u 3 e d i s - s u b s t c e l e s r e g g i r t xx 1 xxxxx # q r i n a s a 1 v u 3 e d i s - d r a c s t c e l e s r e g g i r t xxx 1 xxxx # q r i n a s a 2 v u 3 e d i s - d r a c s t c e l e s r e g g i r t xxxx 1 xxx # q r i n a s a v o 4 e d i s - s u b s t c e l e s r e g g i r t xxxxx 1 xx # q r i n a s a v u 4 e d i s - s u b s t c e l e s r e g g i r t xxxxxx 1 x # q r i n a s a 1 v u 4 e d i s - d r a c s t c e l e s r e g g i r t xxxxxxx 1 # q r i n a s a 2 v u 4 e d i s - d r a c s t c e l e s r e g g i r t 2049 table08 1.0 2049 table09 1.0
12 SMT4004 2049 2.2 9/13/00 summit microelectronics, inc. irq power-on delay and source select (for all supply managers) crowbar source enables 2049 table10 1.0 2049 table11 1.0 5 1 r r e t s i g e r 7 d6 d5 d4 d3 d2 d1 d0 dn o i t c a x 000 xxxx ) s m 0 ( f f o y a l e d n o r e w o p # q r i x 100 xxxx s m 0 0 2 y a l e d n o r e w o p # q r i x 10 1 xxxx s m 0 0 4 y a l e d n o r e w o p # q r i x 110 xxxx s m 0 0 8 y a l e d n o r e w o p # q r i x 111 xxxx s m 0 0 6 1 y a l e d n o r e w o p # q r i xxxx 1 xxx # q r i s r e g g i r t t n e r r u c - r e v o 1 y l p p u s xxxxx 1 xx # q r i s r e g g i r t t n e r r u c - r e v o 2 y l p p u s xxxxxx 1 x# q r i s r e g g i r t t n e r r u c - r e v o 3 y l p p u s xxxxxxx 1 # q r i s r e g g i r t t n e r r u c - r e v o 4 y l p p u s 9 1 r r e t s i g e r 7 d6 d5 d4 d3 d2 d1 d0 d n o i t c a e c r o f d s _ # q r i _ k r t # q r i 1 t s r1 t s r1 t s r1 t s r k c i u q p i r t 1 xxxxxxx d s _ e c r o f e l b a n e x 1 xxxxxx t p u r r e t n i l a r e n e g xx 1 xxxxx t p u r r e t n i r e k k a r t xxx 1 xxxx t e s e r 1 y l p p u s xxxx 1 xxx t e s e r 2 y l p p u s xxxxx 1 xx t e s e r 3 y l p p u s xxxxxx 1 xt e s e r 4 y l p p u s xxxxxxx 1 n o i t i d n o c p i r t k c i u q
13 2049 2.2 9/13/00 SMT4004 summit microelectronics, inc. quick-trip voltage thresholds over-current delay and active pin level select 2049 table12 1.0 2049 table13 1.0 a 1 r r e t s i g e r 7 d6 d5 d4 d3 d2 d1 d0 d n o i t c a 1 r e g a n a m2 r e g a n a m3 r e g a n a m4 r e g a n a m 00 x f f o 01 v m 5 7 10 v m 0 0 1 11 v m 0 5 1 x 00 x f f o 01 v m 5 7 10 v m 0 0 1 11 v m 0 5 1 x 00 x f f o 01 v m 5 7 10 v m 0 0 1 11 v m 0 5 1 x 00 f f o 01 v m 5 7 10 v m 0 0 1 11 v m 0 5 1 b 1 r r e t s i g e r 7 d6 d5 d4 d3 d2 d1 d0 d n o i t c a a na nb cn eo pd s - fy l d - c o xx 1 xxxxx ) h g i h e v i t c a = 1 ( t u p t u o t l u a f b c x 1 xxxx ) h g i h e v i t c a = 1 ( t u p n i e l b a n e xx 1 xxx ) h g i h e v i t c a = 1 ( t u p n i n o _ r w p xxx 1 xx ) h g i h e v i t c a = 1 ( t u p n i d s _ e c r o f y a l e d t n e r r u c - r e v o xx xxxx 00 s 5 2 xxxx 01 s 0 5 xxxx 10 s 0 0 1 xxxx 11 s 0 0 2
14 SMT4004 2049 2.2 9/13/00 summit microelectronics, inc. timer configuration register 2049 table14 1.0 c 1 r r e t s i g e r 7 d6 d5 d4 d3 d2 d1 d0 d n o i t c a d o i r e p t e s e rr e m i t g o d g n o lr e m i t g o d h c t a w 00 xx s m 5 2 01 s m 0 5 10 s m 0 0 1 11 s m 0 0 2 x 0xx x f f o 100 s m 0 0 8 10 1 s m 0 0 6 1 110 s m 0 0 2 3 111 s m 0 0 4 6 xx 0xx f f o 100 s m 0 0 4 10 1 s m 0 0 8 110 s m 0 0 6 1 111 s m 0 0 2 3
15 2049 2.2 9/13/00 SMT4004 summit microelectronics, inc. status registers 2049 table15 1.0 2049 table16 1.0 2049 table17 1.0 d 1 r s 7 d6 d5 d4 d3 d2 d1 d0 d n o i t c a v u - 1 i vv u - 2 i vv u - 3 i vv u - 4 i vv o - 1 i vv o - 2 i vv o - 3 i vv o - 4 i v 1 xxxxxxx v u 1 e d i s - s u b x 1 xxxxxx v u 2 e d i s - s u b xx 1 xxxxx v u 3 e d i s - s u b xxx 1 xxxx v u 4 e d i s - s u b xxxx 1 xxx v o 1 e d i s - s u b xxxxx 1 xx v o 2 e d i s - s u b xxxxxx 1 xv o 3 e d i s - s u b xxxxxxx 1 v o 4 e d i s - s u b e 1 r s 7 d6 d5 d4 d3 d2 d1 d0 d n o i t c a - 1 o v 1 v u - 2 o v 1 v u - 3 o v 1 v u - 4 o v 1 v u - 1 o v 2 v u - 2 o v 2 v u - 3 o v 2 v u - 4 o v 2 v u 1 xxxxxxx 1 v u 1 e d i s - d r a c x 1 xxxxxx 1 v u 2 e d i s - d r a c xx 1 xxxxx 1 v u 3 e d i s - d r a c xxx 1 xxxx 1 v u 4 e d i s - d r a c xxxx 1 xxx 2 v u 1 e d i s - d r a c xxxxx 1 xx 2 v u 2 e d i s - d r a c xxxxxx 1 x2 v u 3 e d i s - d r a c xxxxxxx 1 2 v u 4 e d i s - d r a c f 1 r s 7 d6 d5 d4 d3 d2 d1 d0 d n o i t c a 1 k r t2 k r t3 k r t4 k r t1 c o2 c o3 c o4 c o 1 xxxxxxx 1 y l p p u s r o r r e r e k k a r t x 1 xxxxxx 2 y l p p u s r o r r e r e k k a r t xx 1 xxxxx 3 y l p p u s r o r r e r e k k a r t xxx 1 xxxx 4 y l p p u s r o r r e r e k k a r t xxxx 1 xxx 1 y l p p u s t n e r r u c - r e v o xxxxx 1 xx 2 y l p p u s t n e r r u c - r e v o xxxxxx 1 x3 y l p p u s t n e r r u c - r e v o xxxxxxx 1 4 y l p p u s t n e r r u c - r e v o
16 SMT4004 2049 2.2 9/13/00 summit microelectronics, inc. ac operating characteristics over recommended operating conditions figure 2. memory operating characteristics 2049 table18 2.0 t f t r t low t high t hd:sda t su:sda t buf t dh t hd:dat t su:dat t su:sto scl sda in sda out t aa 2049 fig02 1.0 l o b m y sr e t e m a r a ps n o i t i d n o c. n i m. x a ms t i n u f l c s y c n e u q e r f k c o l c l c s 00 0 1z h k t w o l d o i r e p w o l k c o l c 7 . 4s t h g i h d o i r e p h g i h k c o l c 0 . 4s t f u b e m i t e e r f s u bn o i s s i m s n a r t w e n e r o f e b7 . 4s t a t s : u s e m i t p u t e s n o i t i d n o c t r a t s 7 . 4s t a t s : d h e m i t d l o h n o i t i d n o c t r a t s 0 . 4s t o t s : u s e m i t p u t e s n o i t i d n o c p o t s 7 . 4s t a a t u p t u o d i l a v o t e g d e k c o l c) n e l c y c ( a d s d i l a v o t w o l l c s3 . 05 . 3s t h d e m i t d l o h t u o a t a de g n a h c a d s o t ) 1 + n e l c y c ( w o l l c s3 . 0s t r e m i t e s i r a d s d n a l c s 0 0 0 1s n t f e m i t l l a f a d s d n a l c s 0 0 3s n t t a d : u s e m i t p u t e s n i a t a d 0 5 2s n t t a d : d h e m i t d l o h n i a t a d 0s n i ta d s d n a l c s r e t l i f e s i o nn o i s s e r p p u s e s i o n0 0 1s n t r w e m i t e l c y c e t i r w 5s m
17 2049 2.2 9/13/00 SMT4004 summit microelectronics, inc. figure 3. read and write operations typical write operation (standard memory device type) a c k r / w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k s t o p s t a r t current address read (alternate memory device type) master sda slave 0 1 0 s t a r t a c k b a 2 b a 1 a 8 r / w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k s t o p master sda slave 0 1 10 a c k r / w a c k d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k s t o p s t a r t writing configuration registers master sda slave 01 10 master sda slave device type address bus address a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 1 c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 a c k r / w a c k s t a r t c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 reading the configuration register 01 10 a c k r / w a c k s t o p s t a r t d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 01 10 up to 15 additional bytes can be written before issuing the stop. the host may continue clocking out data so long as it provides an ack response after each byte. b a 2 b a 1 a 8 b a 2 b a 1 x b a 2 b a 1 x b a 2 b a 1 x 2049 fig03 2.0
18 SMT4004 2049 2.2 9/13/00 summit microelectronics, inc. memory and register operation the trakker has a nonvolatile memory that is config- ured as a 256 x 8 array. configuration registers reside in another ? device type ? address space. all read and write operations to both ? device type ? spaces are handled via an industry standard two-wire interface. the bus was designed for two-way, two-line serial com- munication between different integrated circuits. the two lines are a serial data line (sda), and a serial clock line (scl). the sda line must be connected to a positive supply by a pull-up resistor, located somewhere on the bus data protocol the protocol defines any device that sends data onto the bus as a ? transmitter ? and any device that receives data as a ? receiver. ? the device controlling data transmission is called the ? master ? and the controlled device is called the ? slave. ? the trakker will always be a ? slave ? device since it never initiates a data transfer. one data bit is transferred during each clock pulse. the data on the sda line must remain stable during clock high time, because changes on the data line while scl is high will be interpreted as start or stop condition. start and stop conditions when both the data and clock lines are high, the bus is said to be not busy. a high-to-low transition on the data line, while the clock is high, is defined as the ? start ? condi- tion. a low-to- high transition on the data line while the clock is high is defined as the ? stop ? condition. acknowledge (ack) acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either the master or the slave, will release the bus after transmit- ting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. the trakker will respond with an acknowledge after recognition of a start condition and its slave address byte. if both the device and a write operation are selected the trakker will respond with an acknowledge after the receipt of each subsequent 8-bit word. in the read mode the trakker transmits eight bits of data, releases the sda line, and then monitors the line for an acknowl- edge signal. if an acknowledge is detected, and no stop condition is generated by the master, the trakker will continue to transmit data. if an acknowledge is not detected the trakker will terminate further data trans- missions and await a stop condition before returning to the standby power mode. device addressing following a start condition the master must output the address of the slave it is accessing. the most signifi- cant four bits of the slave address are the device type identifier (see the following table). the next three bits are the physical device address. read/write bit the last bit of the data stream defines the operation to be performed. when set to ? 1, ? a read operation is selected; when set to ? 0, ? a write operation. memory write operations the trakker allows two types of write operations: byte- write and page write. a byte-write operation writes a single byte during the nonvolatile write period (twr). the page write operation allows up to 16 bytes in the same page to be written during t wr . byte write after the slave address is sent (to identify both the slave device and a read or write operation), a second byte is transmitted which contains the 8-bit address of any one of the 256 words in the array. upon receipt of the word address the trakker responds with an acknowledge. after receiving the next byte of data it again responds with an acknowledge. the master then terminates the trans- fer by generating a stop condition, at which time the trakker begins the internal write cycle. while the internal write cycle is in progress the trakker inputs are disabled, and the device will not respond to any requests from the master. 2049 table19 1.0 e p y t e c i v e ds s e r d d a s u bw / r n o i t c a 7 d6 d5 d4 d3 d2 d1 d0 d 10 10 2 a1 a0 a0 / 1 s s e r d d a e p y t - e c i v e d y r o m e m 10 1 1 s s e r d d a e p y t - e c i v e d y r o m e m e t a n r e t l a 10 0 1 s s e r d d a e p y t - e c i v e d s r e t s i g e r n o i t a r u g i f n o c
19 2049 2.2 9/13/00 SMT4004 summit microelectronics, inc. page write the trakker is capable of a 16-byte page-write opera- tion. it is initiated in the same manner as the byte-write operation, but instead of terminating the write cycle after the first data word the master can transmit up to 15 more bytes of data. after the receipt of each byte the trakker will respond with an acknowledge. the trakker automatically increments the address for subsequent data words. after the receipt of each word, the low order address bits are internally incremented by one. the high order bits of the address byte remain constant. should the master transmit more than 16 bytes, prior to generating the stop condition, the address counter will ? roll over ? and the previously written data will be overwrit- ten. as with the byte-write operation, all inputs are disabled during the internal write cycle. refer to figure 3 for the address, acknowledge and data transfer se- quence. acknowledge polling when the trakker is performing an internal write operation it will ignore any new start conditions. since the device will only return an acknowledge after it accepts the start, the part can be continuously queried until an acknowledge is issued, indicating that the internal write cycle is complete. see the flow diagram for the proper sequence of operations for polling. read operations read operations are initiated with the r/w bit of the identification field set to ? 1. ? there are two different read options: 1. current address byte read 2. random address byte read current address read the trakker contains an internal address counter which maintains the address of the last word accessed, incremented by one. if the last address accessed (either a read or write) was to address location n, the next read operation would access data from address location n+1 and increment the current address pointer. when the trakker receives the slave address field with the r/w bit set to ? 1 ? it issues an acknowledge and transmits the 8- bit word stored at address location n+1. the current address byte read operation only accesses a single byte of data. the master does not acknowledge the transfer, but does generate a stop condition. at this point the trakker discontinues data transmission. random address read random address read operations allow the master to access any memory location in a random fashion. this operation involves a two-step process. first, the master issues a write command which includes the start condition and the slave address field (with the r/w bit set to write), followed by the address of the word it is to read. this procedure sets the internal address counter of the trak- ker to the desired address. after the word address acknowledge is received by the it the master immediately reissues a start condition followed by another slave ad- dress field with the r/w bit set to read. the trakker will respond with an acknowledge and then transmit the 8 data bits stored at the addressed location. at this point, the master does not acknowledge the transmission but does generate the stop condition. the trakker discontinues data transmission and reverts to its standby power mode. flow chart next operation a write? ack returned issue address proceed with write await next command issue stop issue slave address and r/w = 0 issue stop write cycle in progress ye s no issue start 2049 flow01 1.0 ye s no
20 SMT4004 2049 2.2 9/13/00 summit microelectronics, inc. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted as with the other byte read modes (current address byte read or random address byte read). however, the master now responds with an acknowl- edge, indicating that it requires additional data from the trakker . the trakker continues to output data for each acknowledge received. the master terminates the sequential read operation by not responding with an acknowledge, and issues a stop condition. during a sequential read operation the internal address counter is automatically incremented with each acknowledge sig- nal. for read operations all address bits are incremented, allowing the entire array to be read using a single read command. after a count of the last memory address the address counter will ? roll-over ? and the memory will con- tinue to output data.
21 2049 2.2 9/13/00 SMT4004 summit microelectronics, inc. application circuit see figure 4. a typical circuit soft starting the 5v supply and trakking the 3.3v, 2.5v and 1.8v supplies figure 4. application circuit vgate4 vgate3 vgate2 vgate1 vo4 vo3 vo2 vo1 vi4 vi3 vi2 vi1 cb4 cb3 cb2 cb1 agnd dgnd pgnd pgnd enable uv_override seated1# pwr_on force_sd seated2# rst1# rst2# rst3# rst4# crowbar vdd_cap SMT4004 raw5v raw3.3v gnd 5v 3.3v 2.5v 1.8v 10 ? 10 ? 10 ? 10 ? 5m ? 2m ? 2.5m ? 2m ? 1.8v @10a 2.5v @4a 10k ? 10k ? 10k ? 10f 4 330f 2 330f 500f 5 220f 100nf 4.7f 4.7f to pullup r s gnd wldi wdo# ldo# mr# irq_clr# 1.25vref trkr_irq# vgg_cap cbfault irq# healthy# a2 a1 a0 scl sda 2049 fig04 2.0
22 SMT4004 2049 2.2 9/13/00 summit microelectronics, inc. ordering information SMT4004 f base part number package f = 48 pin tqfp r e t s i g e rs t n e t n o c x e h: s a d e r u g i f n o c 0 r4 bv 5 . 4 f o d l o h s e r h t o v 1 r9 6v o . 3 f o d l o h s e r h t 1 v 2 r1 4v 2 . 2 f o d l o h s e r h t 2 v 3 r8 2v 7 . 1 f o d l o h s e r h t 3 v 4 r0 6v 5 . 5 o t t e s v o d e l b a n e v o d n a v u 0 v 5 r0 6v 6 . 3 t a t e s v o d e l b a n e v o d n a v u 1 v 6 r2 6v 8 . 2 t a t e s v o d e l b a n e v o d n a v u 2 v 7 r7 6v 5 . 2 t a t e s v o d e l b a n e v o d n a v u 3 v 8 r9 bv 6 . 4 f o d l o h s e r h t o v e d i s d r a c 9 re 6v 1 . 3 f o d l o h s e r h t 1 v e d i s d r a c a r6 4v 3 . 2 f o d l o h s e r h t 2 v e d i s d r a c b rd 2v 8 . 1 f o d l o h s e r h t 3 v e d i s d r a c c r2 av 5 . 4 f o 2 d l o h s e r h t o v e d i s d r a c d r3 av o . 3 f o 2 d l o h s e r h t 1 v e d i s d r a c e r4 av 2 . 2 f o 2 d l o h s e r h t 2 v e d i s d r a c f r6 av 7 . 1 f o 2 d l o h s e r h t 3 v e d i s d r a c 0 1 r5 00 1 0 1 , s e s s e r d d a d e s a i b n i p o t s d n o p s e r n i b f f o d n a n o e t a r w e l s s / v 0 5 2 , 1 1 rf fs e c r u o s t e s e r l l a e l b a n e 2 1 rf fs e c r u o s q r i d n a t e s e r l l a e l b a n e 3 1 rf fs e c r u o s q r i l l a e l b a n e 4 1 rf fs e c r u o s q r i l l a e l b a n e 5 1 rf es e c r u o s l l a e l b a n e , y a l e d q r i o t r o p s m 0 0 8 9 1 r1 8y l n o p i r t k c i u q d n a t u p n i l a u n a m n o r a b w o r c e l b a n e a 1 ra as t i u c r i c r e g a n a m l l a p i r t k c i u q v m 0 0 1 e l b a n e b i r2 0s 0 0 1 y a l e d t n e r r u c r e v o , w o l e v i t c a s t u p t u o l l a c i r6 fs m 0 0 6 1 g o d h c t a w , s m 0 0 2 3 g o d g n o l , s m 0 0 2 t e s e r 2049 reg table 1.0
23 2049 2.2 9/13/00 SMT4004 summit microelectronics, inc. package 48 pin tqfp package notice summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. summit microelectronics, inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user ? s specific application. while the information in this publication has been carefully checked, summit microelectronics, inc. shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. ? copyright 2000 summit microelectronics, inc. i 2 c is a trademark of philips corporation. pin 1 0.50 bsc detail "a" 1 ref detail "b" a b 1.60 max 1.35 ? 1.45 0.22 8.975 ? 9.025 0.353 ? 0.355 6.5 ? 7.1 0.271 ? 0.280 6.5 ? 7.1 0.271 ? 0.280 8.975 ? 9.025 0.353 ? 0.355 0.02 0.063 0.053 ? 0.057 0.10 ? 0.20 0.004 ? 0.008 0.45 ? 0.75 0.018 ? 0.030 0.076 0.003 0.009 mm. in.

▲Up To Search▲

Price & Availability of SMT4004

	To Download SMT4004 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .